1. Field of the Invention
This invention relates to the fabrication of semiconductor devices, and more specifically, to the removal of oxides from the surface of a semiconductor substrate.
2. Description of Related Art
The importance of high quality oxides in the fabrication of semiconductor devices cannot be over-emphasized. Many broad categories of commercial devices, such as Electrically Erasable Programmable Read-Only Memories (EEPROMS), Dynamic Random Access Memories (DRAMs), and more recently, even high-speed basic logic functions, owe their commercialization to the reproducibility of high quality, very thin oxide layers.
FIGS. 1A, 1B, and 1C are cross sections of a portion of a twin-tub CMOS structure which illustrate several steps in the removal of the N-well oxide grown during the drive-in of an N-well implant. FIG. 1A shows the structure immediately after the N-well oxidation. In this example N-well oxide 14 is nominally 2700.ANG. thick, having been grown to this thickness by a previous high temperature drive-in step for diffusing and activating the N-well implant (not shown) to form N-well 22 within bulk semiconductor 17. This specific thickness of 2700.ANG. also provides a useful layer thickness to devise alignment structures for certain lithographic equipment. Nitride 10 covers the P-well region 19 (which will subsequently be implanted to form a P-well) to prevent the implantation of the n-type dopant into the P-well region 19, as well as to prevent the growth of any subsequent oxide over the P-well region 19 during the formation of oxide layer 14 over the N-well 22. Nitride layer 10 is typically 920.ANG. thick.
The nitride layer 10 over the P-well region 19 is next removed with a wet phosphoric acid strip. Because of the extremely high selectivity of phosphoric acid between nitride and oxide, very little oxide is removed during this etch step. Barrier oxide 12 covers the P-well region 19 and provides an etch-stop barrier during this nitride removal process, as the phosphoric acid used to etch the nitride 10 would also etch the silicon substrate itself in the P-well region 19. This barrier oxide 12 is approximately 400.ANG. thick. The structure remaining after nitride 10 removal is shown in FIG. 1B. As very little oxide was removed by the nitride etch step, the nominal thickness of barrier oxide 12 is still 400.ANG., and the nominal thickness of N-well oxide 14 remains at 2700.ANG..
A p-type dopant 11 (also shown in FIG. 1B) is next implanted through the barrier oxide 12 into the P-well region 19. N-well oxide 14 provides a suitably thick barrier which keeps the p-type dopant 11 from reaching the N-well 22. A twin-tub drive-in step follows and activates the p-type implant.
The next step is a 12 minute 10:1 HF dip etch which is required to remove the 2700.ANG. of N-well oxide 14. The resulting structure following the HF dip etch is illustrated in FIG. 1C, which also shows P-well 20 as having been formed in the former P-well region 19. Next, typically the surface is subject to an RCA cleaning, and a thin oxide is subsequently grown over the exposed surface of the semiconductor material. This thin oxide may be a tunnel oxide or a gate oxide, for example.